Module core::arch::mips

source ·

🔬This is a nightly-only experimental API. (stdsimd #27731)

Available on MIPS only.

Expand description

Platform-specific intrinsics for the mips platform.

See the module documentation for more details.

Structs

v2f64ExperimentalMIPS or MIPS-64
v2i64ExperimentalMIPS or MIPS-64
v2u64ExperimentalMIPS or MIPS-64
v4f32ExperimentalMIPS or MIPS-64
v4i32ExperimentalMIPS or MIPS-64
v4u32ExperimentalMIPS or MIPS-64
v8i16ExperimentalMIPS or MIPS-64
v8u16ExperimentalMIPS or MIPS-64
v16i8ExperimentalMIPS or MIPS-64
v16u8ExperimentalMIPS or MIPS-64

Functions

__msa_add_a_b^⚠Experimental(MIPS or MIPS-64) and msa
Vector Add Absolute Values.
__msa_add_a_d^⚠Experimental(MIPS or MIPS-64) and msa
Vector Add Absolute Values
__msa_add_a_h^⚠Experimental(MIPS or MIPS-64) and msa
Vector Add Absolute Values
__msa_add_a_w^⚠Experimental(MIPS or MIPS-64) and msa
Vector Add Absolute Values
__msa_adds_a_b^⚠Experimental(MIPS or MIPS-64) and msa
Signed Saturated Vector Saturated Add of Absolute Values
__msa_adds_a_d^⚠Experimental(MIPS or MIPS-64) and msa
Vector Saturated Add of Absolute Values
__msa_adds_a_h^⚠Experimental(MIPS or MIPS-64) and msa
Vector Saturated Add of Absolute Values
__msa_adds_a_w^⚠Experimental(MIPS or MIPS-64) and msa
Vector Saturated Add of Absolute Values
__msa_adds_s_b^⚠Experimental(MIPS or MIPS-64) and msa
Vector Signed Saturated Add of Signed Values
__msa_adds_s_d^⚠Experimental(MIPS or MIPS-64) and msa
Vector Signed Saturated Add of Signed Values
__msa_adds_s_h^⚠Experimental(MIPS or MIPS-64) and msa
Vector Signed Saturated Add of Signed Values
__msa_adds_s_w^⚠Experimental(MIPS or MIPS-64) and msa
Vector Signed Saturated Add of Signed Values
__msa_adds_u_b^⚠Experimental(MIPS or MIPS-64) and msa
Vector Unsigned Saturated Add of Unsigned Values
__msa_adds_u_d^⚠Experimental(MIPS or MIPS-64) and msa
Vector Unsigned Saturated Add of Unsigned Values
__msa_adds_u_h^⚠Experimental(MIPS or MIPS-64) and msa
Vector Unsigned Saturated Add of Unsigned Values
__msa_adds_u_w^⚠Experimental(MIPS or MIPS-64) and msa
Vector Unsigned Saturated Add of Unsigned Values
__msa_addv_b^⚠Experimental(MIPS or MIPS-64) and msa
Vector Add
__msa_addv_d^⚠Experimental(MIPS or MIPS-64) and msa
Vector Add
__msa_addv_h^⚠Experimental(MIPS or MIPS-64) and msa
Vector Add
__msa_addv_w^⚠Experimental(MIPS or MIPS-64) and msa
Vector Add
__msa_addvi_b^⚠Experimental(MIPS or MIPS-64) and msa
Immediate Add
__msa_addvi_d^⚠Experimental(MIPS or MIPS-64) and msa
Immediate Add
__msa_addvi_h^⚠Experimental(MIPS or MIPS-64) and msa
Immediate Add
__msa_addvi_w^⚠Experimental(MIPS or MIPS-64) and msa
Immediate Add
__msa_and_v^⚠Experimental(MIPS or MIPS-64) and msa
Vector Logical And
__msa_andi_b^⚠Experimental(MIPS or MIPS-64) and msa
Immediate Logical And
__msa_asub_s_b^⚠Experimental(MIPS or MIPS-64) and msa
Vector Absolute Values of Signed Subtract
__msa_asub_s_d^⚠Experimental(MIPS or MIPS-64) and msa
Vector Absolute Values of Signed Subtract
__msa_asub_s_h^⚠Experimental(MIPS or MIPS-64) and msa
Vector Absolute Values of Signed Subtract
__msa_asub_s_w^⚠Experimental(MIPS or MIPS-64) and msa
Vector Absolute Values of Signed Subtract
__msa_asub_u_b^⚠Experimental(MIPS or MIPS-64) and msa
Vector Absolute Values of Unsigned Subtract
__msa_asub_u_d^⚠Experimental(MIPS or MIPS-64) and msa
Vector Absolute Values of Unsigned Subtract
__msa_asub_u_h^⚠Experimental(MIPS or MIPS-64) and msa
Vector Absolute Values of Unsigned Subtract
__msa_asub_u_w^⚠Experimental(MIPS or MIPS-64) and msa
Vector Absolute Values of Unsigned Subtract
__msa_ave_s_b^⚠Experimental(MIPS or MIPS-64) and msa
Vector Signed Average
__msa_ave_s_d^⚠Experimental(MIPS or MIPS-64) and msa
Vector Signed Average
__msa_ave_s_h^⚠Experimental(MIPS or MIPS-64) and msa
Vector Signed Average
__msa_ave_s_w^⚠Experimental(MIPS or MIPS-64) and msa
Vector Signed Average
__msa_ave_u_b^⚠Experimental(MIPS or MIPS-64) and msa
Vector Unsigned Average
__msa_ave_u_d^⚠Experimental(MIPS or MIPS-64) and msa
Vector Unsigned Average
__msa_ave_u_h^⚠Experimental(MIPS or MIPS-64) and msa
Vector Unsigned Average
__msa_ave_u_w^⚠Experimental(MIPS or MIPS-64) and msa
Vector Unsigned Average
__msa_aver_s_b^⚠Experimental(MIPS or MIPS-64) and msa
Vector Signed Average Rounded
__msa_aver_s_d^⚠Experimental(MIPS or MIPS-64) and msa
Vector Signed Average Rounded
__msa_aver_s_h^⚠Experimental(MIPS or MIPS-64) and msa
Vector Signed Average Rounded
__msa_aver_s_w^⚠Experimental(MIPS or MIPS-64) and msa
Vector Signed Average Rounded
__msa_aver_u_b^⚠Experimental(MIPS or MIPS-64) and msa
Vector Unsigned Average Rounded
__msa_aver_u_d^⚠Experimental(MIPS or MIPS-64) and msa
Vector Unsigned Average Rounded
__msa_aver_u_h^⚠Experimental(MIPS or MIPS-64) and msa
Vector Unsigned Average Rounded
__msa_aver_u_w^⚠Experimental(MIPS or MIPS-64) and msa
Vector Unsigned Average Rounded
__msa_bclr_b^⚠Experimental(MIPS or MIPS-64) and msa
Vector Bit Clear
__msa_bclr_d^⚠Experimental(MIPS or MIPS-64) and msa
Vector Bit Clear
__msa_bclr_h^⚠Experimental(MIPS or MIPS-64) and msa
Vector Bit Clear
__msa_bclr_w^⚠Experimental(MIPS or MIPS-64) and msa
Vector Bit Clear
__msa_bclri_b^⚠Experimental(MIPS or MIPS-64) and msa
Immediate Bit Clear
__msa_bclri_d^⚠Experimental(MIPS or MIPS-64) and msa
Immediate Bit Clear
__msa_bclri_h^⚠Experimental(MIPS or MIPS-64) and msa
Immediate Bit Clear
__msa_bclri_w^⚠Experimental(MIPS or MIPS-64) and msa
Immediate Bit Clear
__msa_binsl_b^⚠Experimental(MIPS or MIPS-64) and msa
Vector Bit Insert Left
__msa_binsl_d^⚠Experimental(MIPS or MIPS-64) and msa
Vector Bit Insert Left
__msa_binsl_h^⚠Experimental(MIPS or MIPS-64) and msa
Vector Bit Insert Left
__msa_binsl_w^⚠Experimental(MIPS or MIPS-64) and msa
Vector Bit Insert Left
__msa_binsli_b^⚠Experimental(MIPS or MIPS-64) and msa
Immediate Bit Insert Left
__msa_binsli_d^⚠Experimental(MIPS or MIPS-64) and msa
Immediate Bit Insert Left
__msa_binsli_h^⚠Experimental(MIPS or MIPS-64) and msa
Immediate Bit Insert Left
__msa_binsli_w^⚠Experimental(MIPS or MIPS-64) and msa
Immediate Bit Insert Left
__msa_binsr_b^⚠Experimental(MIPS or MIPS-64) and msa
Vector Bit Insert Right
__msa_binsr_d^⚠Experimental(MIPS or MIPS-64) and msa
Vector Bit Insert Right
__msa_binsr_h^⚠Experimental(MIPS or MIPS-64) and msa
Vector Bit Insert Right
__msa_binsr_w^⚠Experimental(MIPS or MIPS-64) and msa
Vector Bit Insert Right
__msa_binsri_b^⚠Experimental(MIPS or MIPS-64) and msa
Immediate Bit Insert Right
__msa_binsri_d^⚠Experimental(MIPS or MIPS-64) and msa
Immediate Bit Insert Right
__msa_binsri_h^⚠Experimental(MIPS or MIPS-64) and msa
Immediate Bit Insert Right
__msa_binsri_w^⚠Experimental(MIPS or MIPS-64) and msa
Immediate Bit Insert Right
__msa_bmnz_v^⚠Experimental(MIPS or MIPS-64) and msa
Vector Bit Move If Not Zero
__msa_bmnzi_b^⚠Experimental(MIPS or MIPS-64) and msa
Immediate Bit Move If Not Zero
__msa_bmz_v^⚠Experimental(MIPS or MIPS-64) and msa
Vector Bit Move If Zero
__msa_bmzi_b^⚠Experimental(MIPS or MIPS-64) and msa
Immediate Bit Move If Zero
__msa_bneg_b^⚠Experimental(MIPS or MIPS-64) and msa
Vector Bit Negate
__msa_bneg_d^⚠Experimental(MIPS or MIPS-64) and msa
Vector Bit Negate
__msa_bneg_h^⚠Experimental(MIPS or MIPS-64) and msa
Vector Bit Negate
__msa_bneg_w^⚠Experimental(MIPS or MIPS-64) and msa
Vector Bit Negate
__msa_bnegi_b^⚠Experimental(MIPS or MIPS-64) and msa
Immediate Bit Negate
__msa_bnegi_d^⚠Experimental(MIPS or MIPS-64) and msa
Immediate Bit Negate
__msa_bnegi_h^⚠Experimental(MIPS or MIPS-64) and msa
Immediate Bit Negate
__msa_bnegi_w^⚠Experimental(MIPS or MIPS-64) and msa
Immediate Bit Negate
__msa_bnz_b^⚠Experimental(MIPS or MIPS-64) and msa
Immediate Branch If All Elements Are Not Zero
__msa_bnz_d^⚠Experimental(MIPS or MIPS-64) and msa
Immediate Branch If All Elements Are Not Zero
__msa_bnz_h^⚠Experimental(MIPS or MIPS-64) and msa
Immediate Branch If All Elements Are Not Zero
__msa_bnz_v^⚠Experimental(MIPS or MIPS-64) and msa
Immediate Branch If Not Zero (At Least One Element of Any Format Is Not Zero)
__msa_bnz_w^⚠Experimental(MIPS or MIPS-64) and msa
Immediate Branch If All Elements Are Not Zero
__msa_bsel_v^⚠Experimental(MIPS or MIPS-64) and msa
Vector Bit Select
__msa_bseli_b^⚠Experimental(MIPS or MIPS-64) and msa
Immediate Bit Select
__msa_bset_b^⚠Experimental(MIPS or MIPS-64) and msa
Vector Bit Set
__msa_bset_d^⚠Experimental(MIPS or MIPS-64) and msa
Vector Bit Set
__msa_bset_h^⚠Experimental(MIPS or MIPS-64) and msa
Vector Bit Set
__msa_bset_w^⚠Experimental(MIPS or MIPS-64) and msa
Vector Bit Set
__msa_bseti_b^⚠Experimental(MIPS or MIPS-64) and msa
Immediate Bit Set
__msa_bseti_d^⚠Experimental(MIPS or MIPS-64) and msa
Immediate Bit Set
__msa_bseti_h^⚠Experimental(MIPS or MIPS-64) and msa
Immediate Bit Set
__msa_bseti_w^⚠Experimental(MIPS or MIPS-64) and msa
Immediate Bit Set
__msa_bz_b^⚠Experimental(MIPS or MIPS-64) and msa
Immediate Branch If At Least One Element Is Zero
__msa_bz_d^⚠Experimental(MIPS or MIPS-64) and msa
Immediate Branch If At Least One Element Is Zero
__msa_bz_h^⚠Experimental(MIPS or MIPS-64) and msa
Immediate Branch If At Least One Element Is Zero
__msa_bz_v^⚠Experimental(MIPS or MIPS-64) and msa
Immediate Branch If Zero (All Elements of Any Format Are Zero)
__msa_bz_w^⚠Experimental(MIPS or MIPS-64) and msa
Immediate Branch If At Least One Element Is Zero
__msa_ceq_b^⚠Experimental(MIPS or MIPS-64) and msa
Vector Compare Equal
__msa_ceq_d^⚠Experimental(MIPS or MIPS-64) and msa
Vector Compare Equal
__msa_ceq_h^⚠Experimental(MIPS or MIPS-64) and msa
Vector Compare Equal
__msa_ceq_w^⚠Experimental(MIPS or MIPS-64) and msa
Vector Compare Equal
__msa_ceqi_b^⚠Experimental(MIPS or MIPS-64) and msa
Immediate Compare Equal
__msa_ceqi_d^⚠Experimental(MIPS or MIPS-64) and msa
Immediate Compare Equal
__msa_ceqi_h^⚠Experimental(MIPS or MIPS-64) and msa
Immediate Compare Equal
__msa_ceqi_w^⚠Experimental(MIPS or MIPS-64) and msa
Immediate Compare Equal
__msa_cfcmsa^⚠Experimental(MIPS or MIPS-64) and msa
GPR Copy from MSA Control Register
__msa_cle_s_b^⚠Experimental(MIPS or MIPS-64) and msa
Vector Compare Signed Less Than or Equal
__msa_cle_s_d^⚠Experimental(MIPS or MIPS-64) and msa
Vector Compare Signed Less Than or Equal
__msa_cle_s_h^⚠Experimental(MIPS or MIPS-64) and msa
Vector Compare Signed Less Than or Equal
__msa_cle_s_w^⚠Experimental(MIPS or MIPS-64) and msa
Vector Compare Signed Less Than or Equal
__msa_cle_u_b^⚠Experimental(MIPS or MIPS-64) and msa
Vector Compare Unsigned Less Than or Equal
__msa_cle_u_d^⚠Experimental(MIPS or MIPS-64) and msa
Vector Compare Unsigned Less Than or Equal
__msa_cle_u_h^⚠Experimental(MIPS or MIPS-64) and msa
Vector Compare Unsigned Less Than or Equal
__msa_cle_u_w^⚠Experimental(MIPS or MIPS-64) and msa
Vector Compare Unsigned Less Than or Equal
__msa_clei_s_b^⚠Experimental(MIPS or MIPS-64) and msa
Immediate Compare Signed Less Than or Equal
__msa_clei_s_d^⚠Experimental(MIPS or MIPS-64) and msa
Immediate Compare Signed Less Than or Equal
__msa_clei_s_h^⚠Experimental(MIPS or MIPS-64) and msa
Immediate Compare Signed Less Than or Equal
__msa_clei_s_w^⚠Experimental(MIPS or MIPS-64) and msa
Immediate Compare Signed Less Than or Equal
__msa_clei_u_b^⚠Experimental(MIPS or MIPS-64) and msa
Immediate Compare Unsigned Less Than or Equal
__msa_clei_u_d^⚠Experimental(MIPS or MIPS-64) and msa
Immediate Compare Unsigned Less Than or Equal
__msa_clei_u_h^⚠Experimental(MIPS or MIPS-64) and msa
Immediate Compare Unsigned Less Than or Equal
__msa_clei_u_w^⚠Experimental(MIPS or MIPS-64) and msa
Immediate Compare Unsigned Less Than or Equal
__msa_clt_s_b^⚠Experimental(MIPS or MIPS-64) and msa
Vector Compare Signed Less Than
__msa_clt_s_d^⚠Experimental(MIPS or MIPS-64) and msa
Vector Compare Signed Less Than
__msa_clt_s_h^⚠Experimental(MIPS or MIPS-64) and msa
Vector Compare Signed Less Than
__msa_clt_s_w^⚠Experimental(MIPS or MIPS-64) and msa
Vector Compare Signed Less Than
__msa_clt_u_b^⚠Experimental(MIPS or MIPS-64) and msa
Vector Compare Unsigned Less Than
__msa_clt_u_d^⚠Experimental(MIPS or MIPS-64) and msa
Vector Compare Unsigned Less Than
__msa_clt_u_h^⚠Experimental(MIPS or MIPS-64) and msa
Vector Compare Unsigned Less Than
__msa_clt_u_w^⚠Experimental(MIPS or MIPS-64) and msa
Vector Compare Unsigned Less Than
__msa_clti_s_b^⚠Experimental(MIPS or MIPS-64) and msa
Immediate Compare Signed Less Than
__msa_clti_s_d^⚠Experimental(MIPS or MIPS-64) and msa
Immediate Compare Signed Less Than
__msa_clti_s_h^⚠Experimental(MIPS or MIPS-64) and msa
Immediate Compare Signed Less Than
__msa_clti_s_w^⚠Experimental(MIPS or MIPS-64) and msa
Immediate Compare Signed Less Than
__msa_clti_u_b^⚠Experimental(MIPS or MIPS-64) and msa
Immediate Compare Unsigned Less Than
__msa_clti_u_d^⚠Experimental(MIPS or MIPS-64) and msa
Immediate Compare Unsigned Less Than
__msa_clti_u_h^⚠Experimental(MIPS or MIPS-64) and msa
Immediate Compare Unsigned Less Than
__msa_clti_u_w^⚠Experimental(MIPS or MIPS-64) and msa
Immediate Compare Unsigned Less Than
__msa_copy_s_b^⚠Experimental(MIPS or MIPS-64) and msa
Element Copy to GPR Signed
__msa_copy_s_d^⚠Experimental(MIPS or MIPS-64) and msa
Element Copy to GPR Signed
__msa_copy_s_h^⚠Experimental(MIPS or MIPS-64) and msa
Element Copy to GPR Signed
__msa_copy_s_w^⚠Experimental(MIPS or MIPS-64) and msa
Element Copy to GPR Signed
__msa_copy_u_b^⚠Experimental(MIPS or MIPS-64) and msa
Element Copy to GPR Unsigned
__msa_copy_u_d^⚠Experimental(MIPS or MIPS-64) and msa
Element Copy to GPR Unsigned
__msa_copy_u_h^⚠Experimental(MIPS or MIPS-64) and msa
Element Copy to GPR Unsigned
__msa_copy_u_w^⚠Experimental(MIPS or MIPS-64) and msa
Element Copy to GPR Unsigned
__msa_ctcmsa^⚠Experimental(MIPS or MIPS-64) and msa
GPR Copy to MSA Control Register
__msa_div_s_b^⚠Experimental(MIPS or MIPS-64) and msa
Vector Signed Divide
__msa_div_s_d^⚠Experimental(MIPS or MIPS-64) and msa
Vector Signed Divide
__msa_div_s_h^⚠Experimental(MIPS or MIPS-64) and msa
Vector Signed Divide
__msa_div_s_w^⚠Experimental(MIPS or MIPS-64) and msa
Vector Signed Divide
__msa_div_u_b^⚠Experimental(MIPS or MIPS-64) and msa
Vector Unsigned Divide
__msa_div_u_d^⚠Experimental(MIPS or MIPS-64) and msa
Vector Unsigned Divide
__msa_div_u_h^⚠Experimental(MIPS or MIPS-64) and msa
Vector Unsigned Divide
__msa_div_u_w^⚠Experimental(MIPS or MIPS-64) and msa
Vector Unsigned Divide
__msa_dotp_s_d^⚠Experimental(MIPS or MIPS-64) and msa
Vector Signed Dot Product
__msa_dotp_s_h^⚠Experimental(MIPS or MIPS-64) and msa
Vector Signed Dot Product
__msa_dotp_s_w^⚠Experimental(MIPS or MIPS-64) and msa
Vector Signed Dot Product
__msa_dotp_u_d^⚠Experimental(MIPS or MIPS-64) and msa
Vector Unsigned Dot Product
__msa_dotp_u_h^⚠Experimental(MIPS or MIPS-64) and msa
Vector Unsigned Dot Product
__msa_dotp_u_w^⚠Experimental(MIPS or MIPS-64) and msa
Vector Unsigned Dot Product
__msa_dpadd_s_d^⚠Experimental(MIPS or MIPS-64) and msa
Vector Signed Dot Product and Add
__msa_dpadd_s_h^⚠Experimental(MIPS or MIPS-64) and msa
Vector Signed Dot Product and Add
__msa_dpadd_s_w^⚠Experimental(MIPS or MIPS-64) and msa
Vector Signed Dot Product and Add
__msa_dpadd_u_d^⚠Experimental(MIPS or MIPS-64) and msa
Vector Unsigned Dot Product and Add
__msa_dpadd_u_h^⚠Experimental(MIPS or MIPS-64) and msa
Vector Unsigned Dot Product and Add
__msa_dpadd_u_w^⚠Experimental(MIPS or MIPS-64) and msa
Vector Unsigned Dot Product and Add
__msa_dpsub_s_d^⚠Experimental(MIPS or MIPS-64) and msa
Vector Signed Dot Product and Add
__msa_dpsub_s_h^⚠Experimental(MIPS or MIPS-64) and msa
Vector Signed Dot Product and Add
__msa_dpsub_s_w^⚠Experimental(MIPS or MIPS-64) and msa
Vector Signed Dot Product and Add
__msa_dpsub_u_d^⚠Experimental(MIPS or MIPS-64) and msa
Vector Unsigned Dot Product and Add
__msa_dpsub_u_h^⚠Experimental(MIPS or MIPS-64) and msa
Vector Unsigned Dot Product and Add
__msa_dpsub_u_w^⚠Experimental(MIPS or MIPS-64) and msa
Vector Unsigned Dot Product and Add
__msa_fadd_d^⚠Experimental(MIPS or MIPS-64) and msa
Vector Floating-Point Addition
__msa_fadd_w^⚠Experimental(MIPS or MIPS-64) and msa
Vector Floating-Point Addition
__msa_fcaf_d^⚠Experimental(MIPS or MIPS-64) and msa
Vector Floating-Point Quiet Compare Always False
__msa_fcaf_w^⚠Experimental(MIPS or MIPS-64) and msa
Vector Floating-Point Quiet Compare Always False
__msa_fceq_d^⚠Experimental(MIPS or MIPS-64) and msa
Vector Floating-Point Quiet Compare Equal
__msa_fceq_w^⚠Experimental(MIPS or MIPS-64) and msa
Vector Floating-Point Quiet Compare Equal
__msa_fclass_d^⚠Experimental(MIPS or MIPS-64) and msa
Vector Floating-Point Class Mask
__msa_fclass_w^⚠Experimental(MIPS or MIPS-64) and msa
Vector Floating-Point Class Mask
__msa_fcle_d^⚠Experimental(MIPS or MIPS-64) and msa
Vector Floating-Point Quiet Compare Less or Equal
__msa_fcle_w^⚠Experimental(MIPS or MIPS-64) and msa
Vector Floating-Point Quiet Compare Less or Equal
__msa_fclt_d^⚠Experimental(MIPS or MIPS-64) and msa
Vector Floating-Point Quiet Compare Less Than
__msa_fclt_w^⚠Experimental(MIPS or MIPS-64) and msa
Vector Floating-Point Quiet Compare Less Than
__msa_fcne_d^⚠Experimental(MIPS or MIPS-64) and msa
Vector Floating-Point Quiet Compare Not Equal
__msa_fcne_w^⚠Experimental(MIPS or MIPS-64) and msa
Vector Floating-Point Quiet Compare Not Equal
__msa_fcor_d^⚠Experimental(MIPS or MIPS-64) and msa
Vector Floating-Point Quiet Compare Ordered
__msa_fcor_w^⚠Experimental(MIPS or MIPS-64) and msa
Vector Floating-Point Quiet Compare Ordered
__msa_fcueq_d^⚠Experimental(MIPS or MIPS-64) and msa
Vector Floating-Point Quiet Compare Unordered or Equal
__msa_fcueq_w^⚠Experimental(MIPS or MIPS-64) and msa
Vector Floating-Point Quiet Compare Unordered or Equal
__msa_fcule_d^⚠Experimental(MIPS or MIPS-64) and msa
Vector Floating-Point Quiet Compare Unordered or Less or Equal
__msa_fcule_w^⚠Experimental(MIPS or MIPS-64) and msa
Vector Floating-Point Quiet Compare Unordered or Less or Equal
__msa_fcult_d^⚠Experimental(MIPS or MIPS-64) and msa
Vector Floating-Point Quiet Compare Unordered or Less Than
__msa_fcult_w^⚠Experimental(MIPS or MIPS-64) and msa
Vector Floating-Point Quiet Compare Unordered or Less Than
__msa_fcun_d^⚠Experimental(MIPS or MIPS-64) and msa
Vector Floating-Point Quiet Compare Unordered
__msa_fcun_w^⚠Experimental(MIPS or MIPS-64) and msa
Vector Floating-Point Quiet Compare Unordered
__msa_fcune_d^⚠Experimental(MIPS or MIPS-64) and msa
Vector Floating-Point Quiet Compare Unordered or Not Equal
__msa_fcune_w^⚠Experimental(MIPS or MIPS-64) and msa
Vector Floating-Point Quiet Compare Unordered or Not Equal
__msa_fdiv_d^⚠Experimental(MIPS or MIPS-64) and msa
Vector Floating-Point Division
__msa_fdiv_w^⚠Experimental(MIPS or MIPS-64) and msa
Vector Floating-Point Division
__msa_fexdo_w^⚠Experimental(MIPS or MIPS-64) and msa
Vector Floating-Point Down-Convert Interchange Format
__msa_fexp2_d^⚠Experimental(MIPS or MIPS-64) and msa
Vector Floating-Point Down-Convert Interchange Format
__msa_fexp2_w^⚠Experimental(MIPS or MIPS-64) and msa
Vector Floating-Point Down-Convert Interchange Format
__msa_fexupl_d^⚠Experimental(MIPS or MIPS-64) and msa
Vector Floating-Point Up-Convert Interchange Format Left
__msa_fexupr_d^⚠Experimental(MIPS or MIPS-64) and msa
Vector Floating-Point Up-Convert Interchange Format Left
__msa_ffint_s_d^⚠Experimental(MIPS or MIPS-64) and msa
Vector Floating-Point Round and Convert from Signed Integer
__msa_ffint_s_w^⚠Experimental(MIPS or MIPS-64) and msa
Vector Floating-Point Round and Convert from Signed Integer
__msa_ffint_u_d^⚠Experimental(MIPS or MIPS-64) and msa
Vector Floating-Point Round and Convert from Unsigned Integer
__msa_ffint_u_w^⚠Experimental(MIPS or MIPS-64) and msa
Vector Floating-Point Round and Convert from Unsigned Integer
__msa_ffql_d^⚠Experimental(MIPS or MIPS-64) and msa
Vector Floating-Point Convert from Fixed-Point Left
__msa_ffql_w^⚠Experimental(MIPS or MIPS-64) and msa
Vector Floating-Point Convert from Fixed-Point Left
__msa_ffqr_d^⚠Experimental(MIPS or MIPS-64) and msa
Vector Floating-Point Convert from Fixed-Point Left
__msa_ffqr_w^⚠Experimental(MIPS or MIPS-64) and msa
Vector Floating-Point Convert from Fixed-Point Left
__msa_fill_b^⚠Experimental(MIPS or MIPS-64) and msa
Vector Fill from GPR
__msa_fill_d^⚠Experimental(MIPS or MIPS-64) and msa
Vector Fill from GPR
__msa_fill_h^⚠Experimental(MIPS or MIPS-64) and msa
Vector Fill from GPR
__msa_fill_w^⚠Experimental(MIPS or MIPS-64) and msa
Vector Fill from GPR
__msa_flog2_d^⚠Experimental(MIPS or MIPS-64) and msa
Vector Floating-Point Base 2 Logarithm
__msa_flog2_w^⚠Experimental(MIPS or MIPS-64) and msa
Vector Floating-Point Base 2 Logarithm
__msa_fmadd_d^⚠Experimental(MIPS or MIPS-64) and msa
Vector Floating-Point Multiply-Add
__msa_fmadd_w^⚠Experimental(MIPS or MIPS-64) and msa
Vector Floating-Point Multiply-Add
__msa_fmax_a_d^⚠Experimental(MIPS or MIPS-64) and msa
Vector Floating-Point Maximum Based on Absolute Values
__msa_fmax_a_w^⚠Experimental(MIPS or MIPS-64) and msa
Vector Floating-Point Maximum Based on Absolute Values
__msa_fmax_d^⚠Experimental(MIPS or MIPS-64) and msa
Vector Floating-Point Maximum
__msa_fmax_w^⚠Experimental(MIPS or MIPS-64) and msa
Vector Floating-Point Maximum
__msa_fmin_a_d^⚠Experimental(MIPS or MIPS-64) and msa
Vector Floating-Point Minimum Based on Absolute Values
__msa_fmin_a_w^⚠Experimental(MIPS or MIPS-64) and msa
Vector Floating-Point Minimum Based on Absolute Values
__msa_fmin_d^⚠Experimental(MIPS or MIPS-64) and msa
Vector Floating-Point Minimum
__msa_fmin_w^⚠Experimental(MIPS or MIPS-64) and msa
Vector Floating-Point Minimum
__msa_fmsub_d^⚠Experimental(MIPS or MIPS-64) and msa
Vector Floating-Point Multiply-Sub
__msa_fmsub_w^⚠Experimental(MIPS or MIPS-64) and msa
Vector Floating-Point Multiply-Sub
__msa_fmul_d^⚠Experimental(MIPS or MIPS-64) and msa
Vector Floating-Point Multiplication
__msa_fmul_w^⚠Experimental(MIPS or MIPS-64) and msa
Vector Floating-Point Multiplication
__msa_frcp_d^⚠Experimental(MIPS or MIPS-64) and msa
Vector Approximate Floating-Point Reciprocal
__msa_frcp_w^⚠Experimental(MIPS or MIPS-64) and msa
Vector Approximate Floating-Point Reciprocal
__msa_frint_d^⚠Experimental(MIPS or MIPS-64) and msa
Vector Floating-Point Round to Integer
__msa_frint_w^⚠Experimental(MIPS or MIPS-64) and msa
Vector Floating-Point Round to Integer
__msa_frsqrt_d^⚠Experimental(MIPS or MIPS-64) and msa
Vector Approximate Floating-Point Reciprocal of Square Root
__msa_frsqrt_w^⚠Experimental(MIPS or MIPS-64) and msa
Vector Approximate Floating-Point Reciprocal of Square Root
__msa_fsaf_d^⚠Experimental(MIPS or MIPS-64) and msa
Vector Floating-Point Signaling Compare Always False
__msa_fsaf_w^⚠Experimental(MIPS or MIPS-64) and msa
Vector Floating-Point Signaling Compare Always False
__msa_fseq_d^⚠Experimental(MIPS or MIPS-64) and msa
Vector Floating-Point Signaling Compare Equal
__msa_fseq_w^⚠Experimental(MIPS or MIPS-64) and msa
Vector Floating-Point Signaling Compare Equal
__msa_fsle_d^⚠Experimental(MIPS or MIPS-64) and msa
Vector Floating-Point Signaling Compare Less or Equal
__msa_fsle_w^⚠Experimental(MIPS or MIPS-64) and msa
Vector Floating-Point Signaling Compare Less or Equal
__msa_fslt_d^⚠Experimental(MIPS or MIPS-64) and msa
Vector Floating-Point Signaling Compare Less Than
__msa_fslt_w^⚠Experimental(MIPS or MIPS-64) and msa
Vector Floating-Point Signaling Compare Less Than
__msa_fsne_d^⚠Experimental(MIPS or MIPS-64) and msa
Vector Floating-Point Signaling Compare Not Equal
__msa_fsne_w^⚠Experimental(MIPS or MIPS-64) and msa
Vector Floating-Point Signaling Compare Not Equal
__msa_fsor_d^⚠Experimental(MIPS or MIPS-64) and msa
Vector Floating-Point Signaling Compare Ordered
__msa_fsor_w^⚠Experimental(MIPS or MIPS-64) and msa
Vector Floating-Point Signaling Compare Ordered
__msa_fsqrt_d^⚠Experimental(MIPS or MIPS-64) and msa
Vector Floating-Point Square Root
__msa_fsqrt_w^⚠Experimental(MIPS or MIPS-64) and msa
Vector Floating-Point Square Root
__msa_fsub_d^⚠Experimental(MIPS or MIPS-64) and msa
Vector Floating-Point Subtraction
__msa_fsub_w^⚠Experimental(MIPS or MIPS-64) and msa
Vector Floating-Point Subtraction
__msa_fsueq_d^⚠Experimental(MIPS or MIPS-64) and msa
Vector Floating-Point Signaling Compare Ordered
__msa_fsueq_w^⚠Experimental(MIPS or MIPS-64) and msa
Vector Floating-Point Signaling Compare Ordered
__msa_fsule_d^⚠Experimental(MIPS or MIPS-64) and msa
Vector Floating-Point Signaling Compare Unordered or Less or Equal
__msa_fsule_w^⚠Experimental(MIPS or MIPS-64) and msa
Vector Floating-Point Signaling Compare Unordered or Less or Equal
__msa_fsult_d^⚠Experimental(MIPS or MIPS-64) and msa
Vector Floating-Point Signaling Compare Unordered or Less Than
__msa_fsult_w^⚠Experimental(MIPS or MIPS-64) and msa
Vector Floating-Point Signaling Compare Unordered or Less Than
__msa_fsun_d^⚠Experimental(MIPS or MIPS-64) and msa
Vector Floating-Point Signaling Compare Unordered
__msa_fsun_w^⚠Experimental(MIPS or MIPS-64) and msa
Vector Floating-Point Signaling Compare Unordered
__msa_fsune_d^⚠Experimental(MIPS or MIPS-64) and msa
Vector Floating-Point Signaling Compare Unordered or Not Equal
__msa_fsune_w^⚠Experimental(MIPS or MIPS-64) and msa
Vector Floating-Point Signaling Compare Unordered or Not Equal
__msa_ftint_s_d^⚠Experimental(MIPS or MIPS-64) and msa
Vector Floating-Point Convert to Signed Integer
__msa_ftint_s_w^⚠Experimental(MIPS or MIPS-64) and msa
Vector Floating-Point Convert to Signed Integer
__msa_ftint_u_d^⚠Experimental(MIPS or MIPS-64) and msa
Vector Floating-Point Convert to Unsigned Integer
__msa_ftint_u_w^⚠Experimental(MIPS or MIPS-64) and msa
Vector Floating-Point Convert to Unsigned Integer
__msa_ftq_h^⚠Experimental(MIPS or MIPS-64) and msa
Vector Floating-Point Convert to Fixed-Point
__msa_ftq_w^⚠Experimental(MIPS or MIPS-64) and msa
Vector Floating-Point Convert to Fixed-Point
__msa_ftrunc_s_d^⚠Experimental(MIPS or MIPS-64) and msa
Vector Floating-Point Truncate and Convert to Signed Integer
__msa_ftrunc_s_w^⚠Experimental(MIPS or MIPS-64) and msa
Vector Floating-Point Truncate and Convert to Signed Integer
__msa_ftrunc_u_d^⚠Experimental(MIPS or MIPS-64) and msa
Vector Floating-Point Truncate and Convert to Unsigned Integer
__msa_ftrunc_u_w^⚠Experimental(MIPS or MIPS-64) and msa
Vector Floating-Point Truncate and Convert to Unsigned Integer
__msa_hadd_s_d^⚠Experimental(MIPS or MIPS-64) and msa
Vector Signed Horizontal Add
__msa_hadd_s_h^⚠Experimental(MIPS or MIPS-64) and msa
Vector Signed Horizontal Add
__msa_hadd_s_w^⚠Experimental(MIPS or MIPS-64) and msa
Vector Signed Horizontal Add
__msa_hadd_u_d^⚠Experimental(MIPS or MIPS-64) and msa
Vector Unsigned Horizontal Add
__msa_hadd_u_h^⚠Experimental(MIPS or MIPS-64) and msa
Vector Unsigned Horizontal Add
__msa_hadd_u_w^⚠Experimental(MIPS or MIPS-64) and msa
Vector Unsigned Horizontal Add
__msa_hsub_s_d^⚠Experimental(MIPS or MIPS-64) and msa
Vector Signed Horizontal Subtract
__msa_hsub_s_h^⚠Experimental(MIPS or MIPS-64) and msa
Vector Signed Horizontal Subtract
__msa_hsub_s_w^⚠Experimental(MIPS or MIPS-64) and msa
Vector Signed Horizontal Subtract
__msa_hsub_u_d^⚠Experimental(MIPS or MIPS-64) and msa
Vector Unsigned Horizontal Subtract
__msa_hsub_u_h^⚠Experimental(MIPS or MIPS-64) and msa
Vector Unsigned Horizontal Subtract
__msa_hsub_u_w^⚠Experimental(MIPS or MIPS-64) and msa
Vector Unsigned Horizontal Subtract
__msa_ilvev_b^⚠Experimental(MIPS or MIPS-64) and msa
Vector Interleave Even
__msa_ilvev_d^⚠Experimental(MIPS or MIPS-64) and msa
Vector Interleave Even
__msa_ilvev_h^⚠Experimental(MIPS or MIPS-64) and msa
Vector Interleave Even
__msa_ilvev_w^⚠Experimental(MIPS or MIPS-64) and msa
Vector Interleave Even
__msa_ilvl_b^⚠Experimental(MIPS or MIPS-64) and msa
Vector Interleave Left
__msa_ilvl_d^⚠Experimental(MIPS or MIPS-64) and msa
Vector Interleave Left
__msa_ilvl_h^⚠Experimental(MIPS or MIPS-64) and msa
Vector Interleave Left
__msa_ilvl_w^⚠Experimental(MIPS or MIPS-64) and msa
Vector Interleave Left
__msa_ilvod_b^⚠Experimental(MIPS or MIPS-64) and msa
Vector Interleave Odd
__msa_ilvod_d^⚠Experimental(MIPS or MIPS-64) and msa
Vector Interleave Odd
__msa_ilvod_h^⚠Experimental(MIPS or MIPS-64) and msa
Vector Interleave Odd
__msa_ilvod_w^⚠Experimental(MIPS or MIPS-64) and msa
Vector Interleave Odd
__msa_ilvr_b^⚠Experimental(MIPS or MIPS-64) and msa
Vector Interleave Right
__msa_ilvr_d^⚠Experimental(MIPS or MIPS-64) and msa
Vector Interleave Right
__msa_ilvr_h^⚠Experimental(MIPS or MIPS-64) and msa
Vector Interleave Right
__msa_ilvr_w^⚠Experimental(MIPS or MIPS-64) and msa
Vector Interleave Right
__msa_insert_b^⚠Experimental(MIPS or MIPS-64) and msa
GPR Insert Element
__msa_insert_d^⚠Experimental(MIPS or MIPS-64) and msa
GPR Insert Element
__msa_insert_h^⚠Experimental(MIPS or MIPS-64) and msa
GPR Insert Element
__msa_insert_w^⚠Experimental(MIPS or MIPS-64) and msa
GPR Insert Element
__msa_insve_b^⚠Experimental(MIPS or MIPS-64) and msa
Element Insert Element
__msa_insve_d^⚠Experimental(MIPS or MIPS-64) and msa
Element Insert Element
__msa_insve_h^⚠Experimental(MIPS or MIPS-64) and msa
Element Insert Element
__msa_insve_w^⚠Experimental(MIPS or MIPS-64) and msa
Element Insert Element
__msa_ld_b^⚠Experimental(MIPS or MIPS-64) and msa
Vector Load
__msa_ld_d^⚠Experimental(MIPS or MIPS-64) and msa
Vector Load
__msa_ld_h^⚠Experimental(MIPS or MIPS-64) and msa
Vector Load
__msa_ld_w^⚠Experimental(MIPS or MIPS-64) and msa
Vector Load
__msa_ldi_b^⚠Experimental(MIPS or MIPS-64) and msa
Immediate Load
__msa_ldi_d^⚠Experimental(MIPS or MIPS-64) and msa
Immediate Load
__msa_ldi_h^⚠Experimental(MIPS or MIPS-64) and msa
Immediate Load
__msa_ldi_w^⚠Experimental(MIPS or MIPS-64) and msa
Immediate Load
__msa_madd_q_h^⚠Experimental(MIPS or MIPS-64) and msa
Vector Fixed-Point Multiply and Add
__msa_madd_q_w^⚠Experimental(MIPS or MIPS-64) and msa
Vector Fixed-Point Multiply and Add
__msa_maddr_q_h^⚠Experimental(MIPS or MIPS-64) and msa
Vector Fixed-Point Multiply and Add Rounded
__msa_maddr_q_w^⚠Experimental(MIPS or MIPS-64) and msa
Vector Fixed-Point Multiply and Add Rounded
__msa_maddv_b^⚠Experimental(MIPS or MIPS-64) and msa
Vector Multiply and Add
__msa_maddv_d^⚠Experimental(MIPS or MIPS-64) and msa
Vector Multiply and Add
__msa_maddv_h^⚠Experimental(MIPS or MIPS-64) and msa
Vector Multiply and Add
__msa_maddv_w^⚠Experimental(MIPS or MIPS-64) and msa
Vector Multiply and Add
__msa_max_a_b^⚠Experimental(MIPS or MIPS-64) and msa
Vector Maximum Based on Absolute Values
__msa_max_a_d^⚠Experimental(MIPS or MIPS-64) and msa
Vector Maximum Based on Absolute Values
__msa_max_a_h^⚠Experimental(MIPS or MIPS-64) and msa
Vector Maximum Based on Absolute Values
__msa_max_a_w^⚠Experimental(MIPS or MIPS-64) and msa
Vector Maximum Based on Absolute Values
__msa_max_s_b^⚠Experimental(MIPS or MIPS-64) and msa
Vector Signed Maximum
__msa_max_s_d^⚠Experimental(MIPS or MIPS-64) and msa
Vector Signed Maximum
__msa_max_s_h^⚠Experimental(MIPS or MIPS-64) and msa
Vector Signed Maximum
__msa_max_s_w^⚠Experimental(MIPS or MIPS-64) and msa
Vector Signed Maximum
__msa_max_u_b^⚠Experimental(MIPS or MIPS-64) and msa
Vector Unsigned Maximum
__msa_max_u_d^⚠Experimental(MIPS or MIPS-64) and msa
Vector Unsigned Maximum
__msa_max_u_h^⚠Experimental(MIPS or MIPS-64) and msa
Vector Unsigned Maximum
__msa_max_u_w^⚠Experimental(MIPS or MIPS-64) and msa
Vector Unsigned Maximum
__msa_maxi_s_b^⚠Experimental(MIPS or MIPS-64) and msa
Immediate Signed Maximum
__msa_maxi_s_d^⚠Experimental(MIPS or MIPS-64) and msa
Immediate Signed Maximum
__msa_maxi_s_h^⚠Experimental(MIPS or MIPS-64) and msa
Immediate Signed Maximum
__msa_maxi_s_w^⚠Experimental(MIPS or MIPS-64) and msa
Immediate Signed Maximum
__msa_maxi_u_b^⚠Experimental(MIPS or MIPS-64) and msa
Immediate Unsigned Maximum
__msa_maxi_u_d^⚠Experimental(MIPS or MIPS-64) and msa
Immediate Unsigned Maximum
__msa_maxi_u_h^⚠Experimental(MIPS or MIPS-64) and msa
Immediate Unsigned Maximum
__msa_maxi_u_w^⚠Experimental(MIPS or MIPS-64) and msa
Immediate Unsigned Maximum
__msa_min_a_b^⚠Experimental(MIPS or MIPS-64) and msa
Vector Minimum Based on Absolute Value
__msa_min_a_d^⚠Experimental(MIPS or MIPS-64) and msa
Vector Minimum Based on Absolute Value
__msa_min_a_h^⚠Experimental(MIPS or MIPS-64) and msa
Vector Minimum Based on Absolute Value
__msa_min_a_w^⚠Experimental(MIPS or MIPS-64) and msa
Vector Minimum Based on Absolute Value
__msa_min_s_b^⚠Experimental(MIPS or MIPS-64) and msa
Vector Signed Minimum
__msa_min_s_d^⚠Experimental(MIPS or MIPS-64) and msa
Vector Signed Minimum
__msa_min_s_h^⚠Experimental(MIPS or MIPS-64) and msa
Vector Signed Minimum
__msa_min_s_w^⚠Experimental(MIPS or MIPS-64) and msa
Vector Signed Minimum
__msa_min_u_b^⚠Experimental(MIPS or MIPS-64) and msa
Vector Unsigned Minimum
__msa_min_u_d^⚠Experimental(MIPS or MIPS-64) and msa
Vector Unsigned Minimum
__msa_min_u_h^⚠Experimental(MIPS or MIPS-64) and msa
Vector Unsigned Minimum
__msa_min_u_w^⚠Experimental(MIPS or MIPS-64) and msa
Vector Unsigned Minimum
__msa_mini_s_b^⚠Experimental(MIPS or MIPS-64) and msa
Immediate Signed Minimum
__msa_mini_s_d^⚠Experimental(MIPS or MIPS-64) and msa
Immediate Signed Minimum
__msa_mini_s_h^⚠Experimental(MIPS or MIPS-64) and msa
Immediate Signed Minimum
__msa_mini_s_w^⚠Experimental(MIPS or MIPS-64) and msa
Immediate Signed Minimum
__msa_mini_u_b^⚠Experimental(MIPS or MIPS-64) and msa
Immediate Unsigned Minimum
__msa_mini_u_d^⚠Experimental(MIPS or MIPS-64) and msa
Immediate Unsigned Minimum
__msa_mini_u_h^⚠Experimental(MIPS or MIPS-64) and msa
Immediate Unsigned Minimum
__msa_mini_u_w^⚠Experimental(MIPS or MIPS-64) and msa
Immediate Unsigned Minimum
__msa_mod_s_b^⚠Experimental(MIPS or MIPS-64) and msa
Vector Signed Modulo
__msa_mod_s_d^⚠Experimental(MIPS or MIPS-64) and msa
Vector Signed Modulo
__msa_mod_s_h^⚠Experimental(MIPS or MIPS-64) and msa
Vector Signed Modulo
__msa_mod_s_w^⚠Experimental(MIPS or MIPS-64) and msa
Vector Signed Modulo
__msa_mod_u_b^⚠Experimental(MIPS or MIPS-64) and msa
Vector Unsigned Modulo
__msa_mod_u_d^⚠Experimental(MIPS or MIPS-64) and msa
Vector Unsigned Modulo
__msa_mod_u_h^⚠Experimental(MIPS or MIPS-64) and msa
Vector Unsigned Modulo
__msa_mod_u_w^⚠Experimental(MIPS or MIPS-64) and msa
Vector Unsigned Modulo
__msa_move_v^⚠Experimental(MIPS or MIPS-64) and msa
Vector Move
__msa_msub_q_h^⚠Experimental(MIPS or MIPS-64) and msa
Vector Fixed-Point Multiply and Subtract
__msa_msub_q_w^⚠Experimental(MIPS or MIPS-64) and msa
Vector Fixed-Point Multiply and Subtract
__msa_msubr_q_h^⚠Experimental(MIPS or MIPS-64) and msa
Vector Fixed-Point Multiply and Subtract Rounded
__msa_msubr_q_w^⚠Experimental(MIPS or MIPS-64) and msa
Vector Fixed-Point Multiply and Subtract Rounded
__msa_msubv_b^⚠Experimental(MIPS or MIPS-64) and msa
Vector Multiply and Subtract
__msa_msubv_d^⚠Experimental(MIPS or MIPS-64) and msa
Vector Multiply and Subtract
__msa_msubv_h^⚠Experimental(MIPS or MIPS-64) and msa
Vector Multiply and Subtract
__msa_msubv_w^⚠Experimental(MIPS or MIPS-64) and msa
Vector Multiply and Subtract
__msa_mul_q_h^⚠Experimental(MIPS or MIPS-64) and msa
Vector Fixed-Point Multiply
__msa_mul_q_w^⚠Experimental(MIPS or MIPS-64) and msa
Vector Fixed-Point Multiply
__msa_mulr_q_h^⚠Experimental(MIPS or MIPS-64) and msa
Vector Fixed-Point Multiply Rounded
__msa_mulr_q_w^⚠Experimental(MIPS or MIPS-64) and msa
Vector Fixed-Point Multiply Rounded
__msa_mulv_b^⚠Experimental(MIPS or MIPS-64) and msa
Vector Multiply
__msa_mulv_d^⚠Experimental(MIPS or MIPS-64) and msa
Vector Multiply
__msa_mulv_h^⚠Experimental(MIPS or MIPS-64) and msa
Vector Multiply
__msa_mulv_w^⚠Experimental(MIPS or MIPS-64) and msa
Vector Multiply
__msa_nloc_b^⚠Experimental(MIPS or MIPS-64) and msa
Vector Leading Ones Count
__msa_nloc_d^⚠Experimental(MIPS or MIPS-64) and msa
Vector Leading Ones Count
__msa_nloc_h^⚠Experimental(MIPS or MIPS-64) and msa
Vector Leading Ones Count
__msa_nloc_w^⚠Experimental(MIPS or MIPS-64) and msa
Vector Leading Ones Count
__msa_nlzc_b^⚠Experimental(MIPS or MIPS-64) and msa
Vector Leading Zeros Count
__msa_nlzc_d^⚠Experimental(MIPS or MIPS-64) and msa
Vector Leading Zeros Count
__msa_nlzc_h^⚠Experimental(MIPS or MIPS-64) and msa
Vector Leading Zeros Count
__msa_nlzc_w^⚠Experimental(MIPS or MIPS-64) and msa
Vector Leading Zeros Count
__msa_nor_v^⚠Experimental(MIPS or MIPS-64) and msa
Vector Logical Negated Or
__msa_nori_b^⚠Experimental(MIPS or MIPS-64) and msa
Immediate Logical Negated Or
__msa_or_v^⚠Experimental(MIPS or MIPS-64) and msa
Vector Logical Or
__msa_ori_b^⚠Experimental(MIPS or MIPS-64) and msa
Immediate Logical Or
__msa_pckev_b^⚠Experimental(MIPS or MIPS-64) and msa
Vector Pack Even
__msa_pckev_d^⚠Experimental(MIPS or MIPS-64) and msa
Vector Pack Even
__msa_pckev_h^⚠Experimental(MIPS or MIPS-64) and msa
Vector Pack Even
__msa_pckev_w^⚠Experimental(MIPS or MIPS-64) and msa
Vector Pack Even
__msa_pckod_b^⚠Experimental(MIPS or MIPS-64) and msa
Vector Pack Odd
__msa_pckod_d^⚠Experimental(MIPS or MIPS-64) and msa
Vector Pack Odd
__msa_pckod_h^⚠Experimental(MIPS or MIPS-64) and msa
Vector Pack Odd
__msa_pckod_w^⚠Experimental(MIPS or MIPS-64) and msa
Vector Pack Odd
__msa_pcnt_b^⚠Experimental(MIPS or MIPS-64) and msa
Vector Population Count
__msa_pcnt_d^⚠Experimental(MIPS or MIPS-64) and msa
Vector Population Count
__msa_pcnt_h^⚠Experimental(MIPS or MIPS-64) and msa
Vector Population Count
__msa_pcnt_w^⚠Experimental(MIPS or MIPS-64) and msa
Vector Population Count
__msa_sat_s_b^⚠Experimental(MIPS or MIPS-64) and msa
Immediate Signed Saturate
__msa_sat_s_d^⚠Experimental(MIPS or MIPS-64) and msa
Immediate Signed Saturate
__msa_sat_s_h^⚠Experimental(MIPS or MIPS-64) and msa
Immediate Signed Saturate
__msa_sat_s_w^⚠Experimental(MIPS or MIPS-64) and msa
Immediate Signed Saturate
__msa_sat_u_b^⚠Experimental(MIPS or MIPS-64) and msa
Immediate Unsigned Saturate
__msa_sat_u_d^⚠Experimental(MIPS or MIPS-64) and msa
Immediate Unsigned Saturate
__msa_sat_u_h^⚠Experimental(MIPS or MIPS-64) and msa
Immediate Unsigned Saturate
__msa_sat_u_w^⚠Experimental(MIPS or MIPS-64) and msa
Immediate Unsigned Saturate
__msa_shf_b^⚠Experimental(MIPS or MIPS-64) and msa
Immediate Set Shuffle Elements
__msa_shf_h^⚠Experimental(MIPS or MIPS-64) and msa
Immediate Set Shuffle Elements
__msa_shf_w^⚠Experimental(MIPS or MIPS-64) and msa
Immediate Set Shuffle Elements
__msa_sld_b^⚠Experimental(MIPS or MIPS-64) and msa
GPR Columns Slide
__msa_sld_d^⚠Experimental(MIPS or MIPS-64) and msa
GPR Columns Slide
__msa_sld_h^⚠Experimental(MIPS or MIPS-64) and msa
GPR Columns Slide
__msa_sld_w^⚠Experimental(MIPS or MIPS-64) and msa
GPR Columns Slide
__msa_sldi_b^⚠Experimental(MIPS or MIPS-64) and msa
Immediate Columns Slide
__msa_sldi_d^⚠Experimental(MIPS or MIPS-64) and msa
Immediate Columns Slide
__msa_sldi_h^⚠Experimental(MIPS or MIPS-64) and msa
Immediate Columns Slide
__msa_sldi_w^⚠Experimental(MIPS or MIPS-64) and msa
Immediate Columns Slide
__msa_sll_b^⚠Experimental(MIPS or MIPS-64) and msa
Vector Shift Left
__msa_sll_d^⚠Experimental(MIPS or MIPS-64) and msa
Vector Shift Left
__msa_sll_h^⚠Experimental(MIPS or MIPS-64) and msa
Vector Shift Left
__msa_sll_w^⚠Experimental(MIPS or MIPS-64) and msa
Vector Shift Left
__msa_slli_b^⚠Experimental(MIPS or MIPS-64) and msa
Immediate Shift Left
__msa_slli_d^⚠Experimental(MIPS or MIPS-64) and msa
Immediate Shift Left
__msa_slli_h^⚠Experimental(MIPS or MIPS-64) and msa
Immediate Shift Left
__msa_slli_w^⚠Experimental(MIPS or MIPS-64) and msa
Immediate Shift Left
__msa_splat_b^⚠Experimental(MIPS or MIPS-64) and msa
GPR Element Splat
__msa_splat_d^⚠Experimental(MIPS or MIPS-64) and msa
GPR Element Splat
__msa_splat_h^⚠Experimental(MIPS or MIPS-64) and msa
GPR Element Splat
__msa_splat_w^⚠Experimental(MIPS or MIPS-64) and msa
GPR Element Splat
__msa_splati_b^⚠Experimental(MIPS or MIPS-64) and msa
Immediate Element Splat
__msa_splati_d^⚠Experimental(MIPS or MIPS-64) and msa
Immediate Element Splat
__msa_splati_h^⚠Experimental(MIPS or MIPS-64) and msa
Immediate Element Splat
__msa_splati_w^⚠Experimental(MIPS or MIPS-64) and msa
Immediate Element Splat
__msa_sra_b^⚠Experimental(MIPS or MIPS-64) and msa
Vector Shift Right Arithmetic
__msa_sra_d^⚠Experimental(MIPS or MIPS-64) and msa
Vector Shift Right Arithmetic
__msa_sra_h^⚠Experimental(MIPS or MIPS-64) and msa
Vector Shift Right Arithmetic
__msa_sra_w^⚠Experimental(MIPS or MIPS-64) and msa
Vector Shift Right Arithmetic
__msa_srai_b^⚠Experimental(MIPS or MIPS-64) and msa
Immediate Shift Right Arithmetic
__msa_srai_d^⚠Experimental(MIPS or MIPS-64) and msa
Immediate Shift Right Arithmetic
__msa_srai_h^⚠Experimental(MIPS or MIPS-64) and msa
Immediate Shift Right Arithmetic
__msa_srai_w^⚠Experimental(MIPS or MIPS-64) and msa
Immediate Shift Right Arithmetic
__msa_srar_b^⚠Experimental(MIPS or MIPS-64) and msa
Vector Shift Right Arithmetic Rounded
__msa_srar_d^⚠Experimental(MIPS or MIPS-64) and msa
Vector Shift Right Arithmetic Rounded
__msa_srar_h^⚠Experimental(MIPS or MIPS-64) and msa
Vector Shift Right Arithmetic Rounded
__msa_srar_w^⚠Experimental(MIPS or MIPS-64) and msa
Vector Shift Right Arithmetic Rounded
__msa_srari_b^⚠Experimental(MIPS or MIPS-64) and msa
Immediate Shift Right Arithmetic Rounded
__msa_srari_d^⚠Experimental(MIPS or MIPS-64) and msa
Immediate Shift Right Arithmetic Rounded
__msa_srari_h^⚠Experimental(MIPS or MIPS-64) and msa
Immediate Shift Right Arithmetic Rounded
__msa_srari_w^⚠Experimental(MIPS or MIPS-64) and msa
Immediate Shift Right Arithmetic Rounded
__msa_srl_b^⚠Experimental(MIPS or MIPS-64) and msa
Vector Shift Right Logical
__msa_srl_d^⚠Experimental(MIPS or MIPS-64) and msa
Vector Shift Right Logical
__msa_srl_h^⚠Experimental(MIPS or MIPS-64) and msa
Vector Shift Right Logical
__msa_srl_w^⚠Experimental(MIPS or MIPS-64) and msa
Vector Shift Right Logical
__msa_srli_b^⚠Experimental(MIPS or MIPS-64) and msa
Immediate Shift Right Logical
__msa_srli_d^⚠Experimental(MIPS or MIPS-64) and msa
Immediate Shift Right Logical
__msa_srli_h^⚠Experimental(MIPS or MIPS-64) and msa
Immediate Shift Right Logical
__msa_srli_w^⚠Experimental(MIPS or MIPS-64) and msa
Immediate Shift Right Logical
__msa_srlr_b^⚠Experimental(MIPS or MIPS-64) and msa
Vector Shift Right Logical Rounded
__msa_srlr_d^⚠Experimental(MIPS or MIPS-64) and msa
Vector Shift Right Logical Rounded
__msa_srlr_h^⚠Experimental(MIPS or MIPS-64) and msa
Vector Shift Right Logical Rounded
__msa_srlr_w^⚠Experimental(MIPS or MIPS-64) and msa
Vector Shift Right Logical Rounded
__msa_srlri_b^⚠Experimental(MIPS or MIPS-64) and msa
Immediate Shift Right Logical Rounded
__msa_srlri_d^⚠Experimental(MIPS or MIPS-64) and msa
Immediate Shift Right Logical Rounded
__msa_srlri_h^⚠Experimental(MIPS or MIPS-64) and msa
Immediate Shift Right Logical Rounded
__msa_srlri_w^⚠Experimental(MIPS or MIPS-64) and msa
Immediate Shift Right Logical Rounded
__msa_st_b^⚠Experimental(MIPS or MIPS-64) and msa
Vector Store
__msa_st_d^⚠Experimental(MIPS or MIPS-64) and msa
Vector Store
__msa_st_h^⚠Experimental(MIPS or MIPS-64) and msa
Vector Store
__msa_st_w^⚠Experimental(MIPS or MIPS-64) and msa
Vector Store
__msa_subs_s_b^⚠Experimental(MIPS or MIPS-64) and msa
Vector Signed Saturated Subtract of Signed Values
__msa_subs_s_d^⚠Experimental(MIPS or MIPS-64) and msa
Vector Signed Saturated Subtract of Signed Values
__msa_subs_s_h^⚠Experimental(MIPS or MIPS-64) and msa
Vector Signed Saturated Subtract of Signed Values
__msa_subs_s_w^⚠Experimental(MIPS or MIPS-64) and msa
Vector Signed Saturated Subtract of Signed Values
__msa_subs_u_b^⚠Experimental(MIPS or MIPS-64) and msa
Vector Unsigned Saturated Subtract of Unsigned Values
__msa_subs_u_d^⚠Experimental(MIPS or MIPS-64) and msa
Vector Unsigned Saturated Subtract of Unsigned Values
__msa_subs_u_h^⚠Experimental(MIPS or MIPS-64) and msa
Vector Unsigned Saturated Subtract of Unsigned Values
__msa_subs_u_w^⚠Experimental(MIPS or MIPS-64) and msa
Vector Unsigned Saturated Subtract of Unsigned Values
__msa_subsus_u_b^⚠Experimental(MIPS or MIPS-64) and msa
Vector Unsigned Saturated Subtract of Signed from Unsigned
__msa_subsus_u_d^⚠Experimental(MIPS or MIPS-64) and msa
Vector Unsigned Saturated Subtract of Signed from Unsigned
__msa_subsus_u_h^⚠Experimental(MIPS or MIPS-64) and msa
Vector Unsigned Saturated Subtract of Signed from Unsigned
__msa_subsus_u_w^⚠Experimental(MIPS or MIPS-64) and msa
Vector Unsigned Saturated Subtract of Signed from Unsigned
__msa_subsuu_s_b^⚠Experimental(MIPS or MIPS-64) and msa
Vector Signed Saturated Subtract of Unsigned Values
__msa_subsuu_s_d^⚠Experimental(MIPS or MIPS-64) and msa
Vector Signed Saturated Subtract of Unsigned Values
__msa_subsuu_s_h^⚠Experimental(MIPS or MIPS-64) and msa
Vector Signed Saturated Subtract of Unsigned Values
__msa_subsuu_s_w^⚠Experimental(MIPS or MIPS-64) and msa
Vector Signed Saturated Subtract of Unsigned Values
__msa_subv_b^⚠Experimental(MIPS or MIPS-64) and msa
Vector Subtract
__msa_subv_d^⚠Experimental(MIPS or MIPS-64) and msa
Vector Subtract
__msa_subv_h^⚠Experimental(MIPS or MIPS-64) and msa
Vector Subtract
__msa_subv_w^⚠Experimental(MIPS or MIPS-64) and msa
Vector Subtract
__msa_subvi_b^⚠Experimental(MIPS or MIPS-64) and msa
Immediate Subtract
__msa_subvi_d^⚠Experimental(MIPS or MIPS-64) and msa
Immediate Subtract
__msa_subvi_h^⚠Experimental(MIPS or MIPS-64) and msa
Immediate Subtract
__msa_subvi_w^⚠Experimental(MIPS or MIPS-64) and msa
Immediate Subtract
__msa_vshf_b^⚠Experimental(MIPS or MIPS-64) and msa
Vector Data Preserving Shuffle
__msa_vshf_d^⚠Experimental(MIPS or MIPS-64) and msa
Vector Data Preserving Shuffle
__msa_vshf_h^⚠Experimental(MIPS or MIPS-64) and msa
Vector Data Preserving Shuffle
__msa_vshf_w^⚠Experimental(MIPS or MIPS-64) and msa
Vector Data Preserving Shuffle
__msa_xor_v^⚠Experimental(MIPS or MIPS-64) and msa
Vector Logical Exclusive Or
__msa_xori_b^⚠Experimental(MIPS or MIPS-64) and msa
Immediate Logical Exclusive Or
break_^⚠ExperimentalMIPS or MIPS-64
Generates the trap instruction BREAK