# Function core::arch::riscv32::sfence_inval_ir

source · [−]

    pub unsafe fn sfence_inval_ir()

🔬This is a nightly-only experimental API. (`stdsimd` #48556)
Available on RISC-V RV32 only.
Expand description

Generates the `SFENCE.INVAL.IR` instruction

This instruction guarantees that any previous SINVAL.VMA instructions executed by the current hart are ordered before subsequent implicit references by that hart to the memory-management data structures.