* Path, Component, Release: cmrf8sf/rel/HSPICE/models/lpnfet_rf.inc, rf8sf_models, pcad_8rf_V131x 
* CMVC Revision: 1.2 06/09/21 15:19:52 
* 
*> IBM CMRF8SF lpnfet_rf 1.5V LP NFET RF subcircuit 
* 
*************************************************************************** 
* 
* SYNTAX: xxx ( d g s b ) lpnfet_rf l = nnn w = nnn 
* 
* REQUIRED: 
* + w = 1.0u <- Total device width (meters) 
* + l = 0.12u<- Device length (meters) 
* OPTIONAL: 
* + nf = 1 <- Number of gate stripes or "fingers" in device 
* + m (par) = 1 <- Number of parallel instances (multiplicity) 
* + as = 0 <- Source diffusion area (meters^2) 
* + ad = 0 <- Drain diffusion area (meters^2) 
* + ps = 0 <- Source diffusion perimeter in (meters) 
* + pd = 0 <- Drain diffusion perimeter in (meters) 
* + nrd = 0 <- Number of squares of drain diffusion 
* + nrs = 0 <- Number of squares of source diffusion 
* + dtemp = 0 <- Device temp rise from ambient (deg C) 
* + lstis = 1 <- Instance flag to control STI stress effects 
* on a local level in conjunction with gstis 
* global flag (0-> no STI stress effects, 
* 1-> w/ STI stress effects) 
* + sa = 0 <- Distance from PC to RX (STI) edge (meters) 
* + sb = 0 <- Distance from PC to RX (STI) edge (meters) 
* + sd = 0 <- Finger to finger spacing for NF>1 (meters) 
* + lnws = 0 <- Instance flag to control Nwell proximity 
* effects on a local level in conjunction with 
* gwells global flag 
* (0-> no Nwell proximity effects, 
* 1-> w/ Nwell proximity effects) 
* 
* Nwell proximity parameters 
* + panw1 = 0 <- Active area within 0 to 0.15um of NW edge 
* + panw2 = 0 <- Active area within 0.15um to 0.325um of NW edge 
* . . 
* . . 
* . . 
* + panw10 = 0 <- Active area within 1.2um to 1.7um of NW edge 
* + plnest = -1 <- Instance flag : nested vs. isolated ACV effect 
* (-1 -> random, default 
* 1 -> nested 
* 0 -> isolated) 
* + plorient = -1 <- Instance flag : horizontal vs. vertical ACV 
* (-1 -> random, default 
* 1 -> vertical 
* 0 -> horizontal) 
* + pld200 = -1 <- Instance flag : ACLV effect within 200um square 
* (-1 -> random, default 
* 1 -> outside 
* 0 -> inside 200um x 200um square) 
* + pwd100 = -1 <- Instance flag : ACWV effect within 100um square 
* (-1 -> random, default 
* 1 -> outside 
* 0 -> inside 100um x 100um square) 
* + rgatemod = 3 <- Gate resistance flag 
* (0-> no gate resistance, 
* 1-> gate resistance w/ no NQS, 
* 2-> gate resistance w/ NQS outside Cov, 
* 3-> gate resistance w/ NQS inside Cov) 
* + ngcon = 2 <- Gate connection switch (1->single-ended, 
* 2->double-ended) 
* + rbodymod = 1 <- Body resistance network flag (0-> network off, 
* 1-> network on) 
* + ring = 2 <- Substrate contact type for RF PCELL 
* + rf_rsub = 1 <- Body resistance multiplier 
* + cwire = 1 <- Wiring capacitance multiplier 
* 
* NOTES: 
* 
* 1. If nrd or nrs are not passed to the model they will default to 0. 
* This will result in 0 ohms of silicided S/D resistance being placed 
* in series with the device model. 
* 
* SUBCIRCUIT SCHEMATIC: 
* 
* | drain 
* o---|-----o------------------o 
* | | | | 
* | cwgd | | 
* | | --- 
* | | ---cwds 
* | | | 
* | | |--- | 
* gate | g1 | | (BSIM4.4 ) | bulk 
* o----/\/\/\--------o-----| |-----(Internal )--)--o 
* rg | | | (Rsub Network) | 
* | | |--- | 
* | | | 
* | | | 
* | | | 
* | cwgs | | 
* | | | | 
* o---|-----o------------------o 
* | source 
* 
* Note: The LDD resistance is accounted for within the BSIM4 model. 
* 
* IBM CONFIDENTIAL 
* (C) 2006 IBM Corporation 
* 
*************************************************************************** 
* 
.subckt lpnfet_rf d g s b PARAMS: w = 1.0u l = 0.12u nf = 1 par = 1 dtemp = 0 
+ as = 0 ps = 0 ad = 0 pd = 0 nrs = 0 nrd = 0 
+ lstis = 1 sa = 0 sb = 0 sd = 0 lnws = 0 
+ panw1 = 0 panw2 = 0 panw3 = 0 panw4 = 0 panw5 = 0 
+ panw6 = 0 panw7 = 0 panw8 = 0 panw9 = 0 panw10 = 0 
+ plnest = -1 plorient = -1 pld200 = -1 pwd100 = -1 
+ rgatemod = 3 ngcon = 2 rbodymod = 1 ring = 2 
+ rf_rsub = 1 cwire = 1 
* 
.param 
+ legacy = { (ring == 99) } ; Switch for legacy PCELL 
+ nfo = { (int((nf+ 1)/2) - int(nf/2)) } ; Switch for odd,even fingers 
* 
* Extrinsic gate resistance calculations (function of w, l, and nf) 
+ wum = { (w/nf)*1e6 } 
+ lum = { l*1e6 } 
* 
+ rlen_a = { lum*(1 + ((nf - 3)/2)) + diff_thn*1e6*((nf - 1)/2) } 
+ rlen_b = { 0.5*lum + (diff_thn*1e6 + lum)*((nf/2) - 1) } 
+ rlen = { nfo*rlen_a + (1-nfo)*rlen_b } 
* 
+ ra_term1 = { 0.81*legacy + 0.91*(1-legacy) } 
+ ra_len = { (ra_term1 + 0.5*lum + (nf == 2)*0.5*lum + (nf>2)*(rlen/3))/(0.4) } 
+ ra_wid = { (2.5*wum + 1.65)*legacy + (1.25*wum + 0.875)*(1-legacy) } 
+ ra = { m1rsi * (ra_len + ra_wid) } 
+ rb = { m1rsi * (4.3*legacy + 3.3*(1-legacy)) } 
+ rcont = { cars * (1/nf) } 
* 
+ rgate = { 0.5*(rb + (1/ngcon)*(ra+ 0.5*rcont)) } 
* 
.param 
* Substrate resistance calculations (function of w, l, and nf) 
+ rhorz = { max(50,((63e6*l + 376)*(4.0e-3/w)/300)) } 
+ rvert = { max(150,((228e-6/l - 296)*(12e-3/w - 50)/1050)) } 
* 
* Gate capacitance calculation (function of w, l, and nf) 
+ cg1 = { 0.2e6*l + 9 } 
+ cg2 = { 18e6*l } 
+ cgate = { ((cg1*cg2/(cg1+ cg2)) + 0.08e6*w - 1.2)*0.5e-15 } 
* 
* Drain-Source capacitance calculation (function of w, l, and nf) 
+ cdsw = { 1.721e5*w + 0.198 } 
+ cdsl = { (3.65e-7/l + 0.1058)*3e-16 } 
* 
x1 d g1 s b lpnfet PARAMS: w = w l = l nf = nf par = par dtemp = dtemp 
+ as = as ad = ad ps = ps pd = pd nrs = nrs nrd = nrd 
+ lstis = lstis sa = sa sb = sb sd = sd lnws = lnws 
+ panw1 = panw1 panw2 = panw2 panw3 = panw3 panw4 = panw4 
+ panw5 = panw5 panw6 = panw6 panw7 = panw7 panw8 = panw8 
+ panw9 = panw9 panw10 = panw10 
+ plnest = plnest plorient = plorient 
+ pld200 = pld200 pwd100 = pwd100 
+ rgatemod = rgatemod ngcon = ngcon 
+ rbodymod = rbodymod rf_rsub = rf_rsub 
+ rbps = rhorz rbpd = rhorz 
+ rbsb = rvert rbpb = rvert rbdb = rvert 
* 
rg g g1 r = rgate 
cwgd g1 d c = { 1e-18 + cgate*cwire } 
cwgs g1 s c = { 1e-18 + cgate*cwire } 
cwds d s c = { 1e-18 + (cdsw*cdsl)*cwire } 
* 
.ends lpnfet_rf 
