* Path, Component, Release: cmos8base/rel/HSPICE/models/esdndsx.inc, tech8_models, mod_cmos8base 
* CMVC Revision: 1.1.1.1 06/07/27 17:21:54 
* 
*> IBM CMRF8SF/BiCMOS8WL esdndsx N+ or Nwell to Substrate Junction Diode for ESD 
* 
*********************************************************************** 
* 
* Model can be used in conjunction with the design system extraction 
* program which calculates/combines junction parasitic capacitance 
* per node. 
* 
* o nwell (c) 
* | or n diffusion 
* + ----------+ 
* | | 
* /\ ---- 
* / \ Gleak /\ Dnwx 
* \ / / \ Diode includes junction capacitance, 
* \/ ---- resistance and sat current parameters. 
* | | 
* + ----------+ 
* | 
* \ 
* / Rseries 
* \ 
* | 
* o substrate (a) 
* 
*********************************************************************** 
* 
* SYNTAX: Specify both total area and perimeter and 'number of cathodes' 
* as well as whether or not N-well is used 
* xxx (a c) esdndsx (areac = 1p pjc = 1u nf = 1 bp = 3 dtemp = 0) 
* 
* 
* NOTES: 
* 
* 1. Node order must be as specified. 
* 
* 2. Input parameters are 
* 
* areac --> Total area of cathode (RX or NW shape) 
* 
* pjc --> Total perimeter of cathode (RX or NW shape) 
* 
* nf --> Number of cathode fingers 
* 
* bp --> N+ /SX (bp = 3) or NW/SX (bp = 1) 
* NW/SX option supported only in BiCMOS8WL 
* default is bp = 3 N+ /SX diode 
* 
* dtemp --> Device temperature difference with respect to 
* the simulated circuit temperature (deg C). 
* 
* 
* IBM CONFIDENTIAL 
* (C) 2004 IBM Corporation 
* 
*********************************************************************** 
* 
.subckt esdndsx a c PARAMS: areac = 1p pjc = 1u nf = 1 bp = 3 dtemp = 0 
* 
* With or without N-well option 
+ nw = { (bp == 1) } 
* Here we calculate the length and width of a cathode strip 
+ chpfr = { nw*0.00 + (1-nw)*0.12u } 
+ alpha = { areac/nf + 2*chpfr*chpfr } 
+ beta = { (2-sqrt(2))*chpfr+ pjc/(4*nf) } 
+ lcathn = { beta + sqrt(abs(beta*beta - alpha)) } 
+ wcathn = { alpha/lcathn } 
+ wcath = { wcathn + delrx } 
+ lcath = { lcathn + delrx } 
* We then determine the total area and perimeter of anode region 
+ acath = { (lcath*wcath - 2*chpfr*chpfr)*nf } 
+ pcath = { (lcath + wcath + 2*sqrt(2)*chpfr - 4*chpfr)*nf*2 } 
* 
* We then calculate the series resistance, starting with the wire resistance 
* nanod is the # of anodes 
+ nanod = { nf+ 1 } 
* acsp is the anode to cathode separation 
+ acsp = { 0.26u } 
+ acspx = { acsp-delrx } 
* wanodn is the anode width 
+ wanod = { wanodn+ delrx } 
* metwid is the M1 wire width 
+ metwid = { 4.00u } 
* ametl/cmetl is the length of the metal wire connecting the anode/cathode 
+ ametl = { (2*acsp+ wanodn+ wcathn)*nf+ wanodn } 
+ cmetl = { (2*acsp+ wanodn+ wcathn)*nf-(2*acsp+ wanodn) } 
* nwires/nawires/ncwires is the # of total/anode/cathode wires 
+ nwires = { int((lcathn+ 0.12u)/4.36u) } 
+ nawires = { max(int(nwires/2),1) } 
+ ncwires = { max(nwires-nawires,1) } 
* rma/rmc is the resistance of the metal wiring to the anode/cathode 
+ rma = { (m2rs*ametl)/(metwid*nawires) } 
+ rmc = { (m2rs*cmetl)/(metwid*ncwires) } 
* rc2 is the resistance through the pw 
+ rc2 = { (pwrs*acspx)/(2*lcath*nf)+ (pwrs*wcath)/(12*lcath*nf)+ (pwrs*wanod)/(6*lcath*nf) } 
* rc3 is the resistance through the vertical pw 
+ rc3 = { rsubc/(lcath*wanod*nanod) } 
+ rtot = { rma+ rc2+ rc3+ rmc } 
* 
* calculate leakage 
+ lk1 = { (nw*lk1a_nw + (1-nw)*lk1a_n)*acath + (nw*lk1p_nw + (1-nw)*lk1p_n)*pcath } 
+ lk3 = { (nw*lk3a_nw + (1-nw)*lk3a_n)*acath + (nw*lk3p_nw + (1-nw)*lk3p_n)*pcath } 

*KRS: Should fix this at the diode model level, eventually, but I'm just going
*KRS: to kludge in a new model (which does NOT account for temperature 
*KRS: effects!) for sidewall currents.  The prodcut jsw*pj gets added to is
*KRS: in the diode model.  Note that there's still a small difference between
*KRS: the Xyce/Hspice results since Hspice simulates at 25C and Xyce at 27C.
*KRS: Also the scaling on 'isw' looks weird because is eventually gets scaled 
*KRS: by 'area', so we have to cancel that factor out
*
*KRS: additional note:  there seems to be a very small difference in Xyce's
*KRS: version of kT/q vs. Hspice's version---enough that the currents vary by
*KRS: about 50% at high junction voltages (1.5V).

.param isw = {(nw*jsw_nw + (1-nw)*jsw_n )*pcath/acath}

* Subcircuit 
*KRS: getting rid of pj and dtemp in diode model below:
dnwa 1 c dnsx area = acath; pj = pcath dtemp = dtemp 
*KRS: have to rewrite gleak as a b-source:
*gleak 1 c cur = { lk1*pwr(V(1,c),1) + lk3*pwr(V(1,c),3) } 
Bleak 1 c I ={lk1*pwr(V(1,c),1) + lk3*pwr(V(1,c),3)}
rser 1 a { rtot } 

* N/NW to SX Diode 
*KRS:  need to comment out a lot of unused parameters in order not to get 
*KRS: seg fault.  Uncommenting them all for now so that seg fault will show up
*KRS: for bugzilla entry.

.model dnsx d 
+ level = 1 
+ dcap = 2 
+ tlev = 0 
+ tlevc = 1 
+ tref = 25 
+ eg = 1.17 
+ xti = 3.0 
+ n = { nw*n_nw + (1-nw)*n_n } 
*KRS: js is an alias for is in spice, not in Xyce:
+ is = { nw*js_nw + (1-nw)*js_n + isw} 
*+ js = { nw*js_nw + (1-nw)*js_n } 
*+ jsw = { nw*jsw_nw + (1-nw)*jsw_n } 
*KRS: cj in spice, cjo in xyce
*+ cj = { nw*cj_nw + (1-nw)*cj_n } 
+ cjo = { nw*cj_nw + (1-nw)*cj_n } 
+ pb = { nw*pb_nw + (1-nw)*pb_n } 
+ mj = { nw*mj_nw + (1-nw)*mj_n } 
+ cjp = { nw*cjsw_nw + (1-nw)*cjsw_n } 
+ php = { nw*pbsw_nw + (1-nw)*pbsw_n } 
+ mjsw = { nw*mjsw_nw + (1-nw)*mjsw_n } 
+ cta = { nw*cta_nw + (1-nw)*cta_n } 
+ tpb = { nw*pta_nw + (1-nw)*pta_n } 
+ ctp = { nw*ctp_nw + (1-nw)*ctp_n } 
+ tphp = { nw*ptp_nw + (1-nw)*ptp_n } 
*KRS:  vb in hspice, bv in xyce:
+ bv = { nw*bd_nw + (1-nw)*bd_n } 
*+ vb = { nw*bd_nw + (1-nw)*bd_n } 

.ends esdndsx 
